(1) Field of Invention
The present invention relates to phase/frequency acquisition systems, and more particularly, to circuitry for improving the acquisition/locking time of phase-locked loops.
(2) Description of Related Art
When a system sends and receives a signal, the system needs to create a local timing reference for the signal to align with. In most applications, a phase-locked loop (PLL) is used to maintain a generated signal in a fixed relationship to a reference signal. PLLs, at power up or initialization, consume a certain amount of time to acquire the “unknown” input signal's phase and frequency. Depending on the characteristics of the system in which the PLL is being used, the acquisition/locking time may range from tenths of a millisecond to seconds. As can be appreciated, decreasing the acquisition/locking time would provide a benefit to many applications.
While some mechanisms have been devised that decrease the acquisition/locking time, the current approaches compromise between band-width/phase noise and acquisition/locking time. The solutions currently available become ineffective when high-Q PLLs are utilized. Furthermore, most systems are designed to take into account the acquisition/locking time of the utilized PLL. However, an increasing number of applications begin to suffer in performance due to set-up times of the PLLs. For example, all transceivers in RADAR and communication systems, which subject the PLLs to power-down or take them out of the transceiver loop during operation, could benefit from a decreased acquisition/locking time.
Direct Digital Synthesis (DDS) has been offered as a technique for improving the acquisition/locking time of a system. However, the constraints on technologies and circuits needed to utilize DDS for high-Q high-frequency carriers are very high. The previous approaches to speed up the PLL acquisition/locking time are within the phase-locked loop itself and are strongly architecture/frequency dependent (and degrade the performance with respect to resulting phase noise).
To date, little has been done in terms of added/improved algorithms to speed-up the acquisition/locking time. Thus, a continuing need exists for circuitry and algorithms that speed-up the acquisition/locking time for phase-locked loops.